
9-2
MCF5307 User’s Manual
Interrupt Controller Registers
The SIM provides the following registers for managing interrupts:
Each potential interrupt source is assigned one of the 10 interrupt control registers
(ICR0–ICR9), which are used to prioritize the interrupt sources.
The interrupt mask register (IMR) provides bits for masking individual interrupt
sources.
The interrupt pending register (IPR) provides bits for indicating when an interrupt
request is being made (regardless of whether it is masked in the IMR).
The autovector register (AVEC) controls whether the SIM supplies an autovector or
executes an external interrupt acknowledge cycle for each IRQ.
The interrupt port assignment register (IRQPAR) provides the level assignment of
the primary external interrupt pins—IRQ5, IRQ3, and IRQ1.
9.2 Interrupt Controller Registers
The interrupt controller register portion of the SIM memory map is shown in
Table 9-2.Each internal interrupt source has its own interrupt control register (ICR0–ICR9), shown in
Table 9-1. Interrupt Controller Registers
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x040
Interrupt pending register (IPR)
[p. 9-6]0x044
0x048
Reserved
Autovector register
Interrupt Control Registers (ICRs) [p. 9-3] 0x04C
Software watchdog
0x050
0x054
Reserved
Table 9-2. Interrupt Control Registers
MBAR Offset
Register
Name
0x04C
ICR0
Software watchdog timer
0x04D
ICR1
Timer0
0x04E
ICR2
Timer1
0x04F
ICR3
I2C
0x050
ICR4
UART0
0x051
ICR5
UART1
0x052
ICR6
DMA0
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