參數(shù)資料
型號: MCF53013CQT240
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PQFP208
封裝: 28 X 28 MM, ROHS COMPLIANT, LQFP-208
文件頁數(shù): 35/62頁
文件大小: 2365K
代理商: MCF53013CQT240
MCF5301x Data Sheet, Rev. 5
Preliminary—Subject to Change Without Notice
Preliminary Electrical Characteristics
Freescale Semiconductor
40
Figure 27. DSPI Classic SPI Timing — Master Mode
DS10
DSPI_SCK to DSPI_SOUT invalid
0
ns
DS11
DSPI_SIN to DSPI_SCK input setup
2
ns
DS12
DSPI_SCK to DSPI_SIN input hold
7
ns
DS13
DSPI_SS active to DSPI_SOUT driven
20
ns
DS14
DSPI_SS inactive to DSPI_SOUT not driven
18
ns
1 Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin
on the odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
2 When in master mode, the baud rate is programmable in DCTARn[DBR], DCTARn[PBR], and DCTARn[BR].
3 This specification assumes a 50/50 duty cycle setting. The duty cycle is programmable in DCTARn[DBR],
DCTARn[CPHA], and DCTARn[PBR].
4 The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
5 The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
Table 26. DSPI Module AC Timing Specifications1 (continued)
Name
Characteristic
Symbol
Min
Max
Unit
Notes
DSPI_PCSn
DSPI_SCK
DSPI_SOUT
DSPI_SIN
DSPI_SCK
(DCTARn[CPOL] = 1)
(DCTARn[CPOL] = 0)
Data
Last Data
First Data
Data
Last Data
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
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