參數(shù)資料
型號： MCF5274VM133
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133 MHz, RISC PROCESSOR, PBGA256
封裝： MAPBGA-256
文件頁數(shù)： 31/44頁
文件大?。?/td> 1242K
代理商： MCF5274VM133
Preliminary Electrical Characteristics
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
37
Table 24 lists specifications for the I2C output timing parameters shown in Figure 21.
Figure 21 shows timing for the values in Table 23 and Table 24.
Figure 21. I2C Input/Output Timings
I8
Start condition setup time (for repeated start condition only)
2 x tCYC
—ns
I9
Stop condition setup time
2 x tCYC
—ns
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I11
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 24. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the I2C_SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 24 are minimum values.
Start condition hold time
6 x tCYC
—ns
I2 1
Clock low period
10 x tCYC
—ns
I3 2
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
I4 1
Data hold time
7 x tCYC
—ns
I5 3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
I6 1
Clock high time
10 x tCYC
—ns
I7 1
Data setup time
2 x tCYC
—ns
I8 1
Start condition setup time (for repeated start
condition only)
20 x tCYC
—ns
I9 1
Stop condition setup time
10 x tCYC
—ns
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
SCL
SDA
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