
Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-36
Freescale Semiconductor
Figure 13-35. Port 1 Configuration Register (P1CR)
The programming of the P1CR register in the above example is achieved with the following ColdFire code
sequence assuming the equates and init sections include the following:
equates and init:
...
Module_Regs_Addr
EQU
0x00300000
;address of on-chip registers
P1CR
EQU
0x352
;offset of P1CR register
P1ICR
EQU
0x35A
...
move.l
#Module_Regs_Addr, A5
;reference register from A5
...
move.w
#0x9200,d0
;port 1 config ON, IDL10, SLAVE, port1 FSM
;msb first on B1 and B2, B1 and B2 disabled
move.w
d0,P1CR(A5)
;write to P1CR register
The above code segment is an example only.
FSM (port 1 Only)
SCIT MODE (GCI ONLY)
SLAVE MODE
IDL10 MODE
Reserved
Port on
Reserved
B2 msb First
B1 msb First
B2 Disabled
B1 Disabled
15 14 13 12 11 10
9876543210
P1CR
1001001000000000
0x
9200
GCI ACT (GCI ONLY)