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Pulse-Width Modulation (PWM) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
18-4
Freescale Semiconductor
18.3.2
PWM Width Register (PWWDn)
This register, shown in
Figure 18-3, controls the width of the output pulse. When the counter become
greater than or equal to the value in this register, the output is cleared for the remainder of the period. When
the counter overflows, or wraps around, the counter value becomes less than or equal to the value of the
width register and the output is set high.
Writing to the width register while the PWM is enabled will not alter the operation of the PWM until the
end of the current output cycle. That is, the width value is not modified until after the counter has wrapped
around. The PWM must be disabled and then re-enabled to affect its operation before the end of the current
output cycle.
Figure 18-3. PWM Width Register (PWWDn)
Figure 18-4 shows example PWM waveforms and their dependence on PWWD[PW].
Figure 18-4. PWM Waveform Examples (PWCRn[EN] = 1)
7
0
Field
PW
Reset
0000_0000
R/W
Address
MBAR + 0x0D0 (PWWD0); + 0x0D4 (PWWD1); + 0x0D8 (PWWD2)
Table 18-3. PWWDn Field Descriptions
Bits
Name
Description
7–0
PW
Pulse width. Range 0x00–0xFF. When the counter value become greater than PWWD[PW], the output is
cleared for the remainder of the period. When the counter overflows, or wraps around, the counter value
becomes less than or equal to PWWD[PW] and the output is set.
256T
T
128T
255T
T
128T
255T
PWWD[PW] = 0x00
PWWD[PW] = 0x01
PWWD[PW] = 0x80
PWWD[PW] = 0xFF
PWCRn[CKSL] = 0000: T = 1 x CPU clock period
PWCRn[CKSL] = 1111: T = 32768 x CPU clock period
PWCRn[FRC1] = 1