
Reg
ister
Mem
o
ry
Map
MCF5
271
Reference
Man
u
al,
Re
v
.2
F
reescale
Sem
ic
o
nductor
A-7
Table A-8. I2C Memory Map
Base Address: IPSBAR
Offset
Page
Register Description
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0300
I2C Address Register
I2ADR
0x00_0304
I2C Frequency Divider Register
I2FDR
0x00_0308
I2C Control Register
I2CR
0x00_030C
I2C Status Register
I2SR
0x00_0310
I2C Data I/O Register
I2DR
Table A-9. QSPI Memory Map
Base Address: IPSBAR
Offset
Page
Register Description
[31:24]
[23:16]
[15:8]
[7:0]
0x00_0340
QSPI Mode Register
QMR
0x00_0344
QSPI Delay Register
QDLYR
0x00_0348
QSPI Wrap Register
QWR
0x00_034C
QSPI Interrupt Register
QIR
0x00_0350
QSPI Address Register
QAR
0x00_0354
QSPI Data Register
QDR
Table A-10. DMA Timer Memory Map
Base Address:
DMA Timer 0: IPSBAR + 0x00_0400
DMA Timer 1: IPSBAR + 0x00_0440
DMA Timer 2: IPSBAR + 0x00_0480
DMA Timer 3: IPSBAR + 0x00_04C0
Offset
Page
Register Description
[31:24]
[23:16]
[15:8]
[7:0]
0x00
DMA Timer n Mode Register
DMA Timer n Extended Mode Register
DMA Timer n Event Register
DTMRn
DTXMRn
DTERn
0x04
DMA Timer n Reference Register
DTRRn