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參數(shù)資料
| 型號： | MCF5232CAB80 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Microprocessor Hardware Specification |
| 中文描述： | 集成的微處理器，硬件規(guī)格 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 988K |
| 代理商： | MCF5232CAB80 |
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MCF523x Integrated Microprocessor Hardware Specification, Rev. 2
Preliminary Electrical Characteristics
Freescale Semiconductor
28
7.5
External Interface Timing Characteristics
Table 11
lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
Timings listed in
Table 11
are shown in
Figure 10
& Figure A-3.
7
This specification applies to the period required for the PLL to relock after changing the MFD frequency
control bits in the synthesizer control register (SYNCR).
Assuming a reference is available at power up, lock time is measured from the time V
DD
and V
DDSYN
are
valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the
crystal start up time must be added to the PLL lock time to determine the total start-up time.
t
lpll
= (64
*
4
*
5 + 5
×
τ
)
×
T
ref
, where T
ref
= 1/F
ref_crystal
= 1/F
ref_ext
= 1/F
ref_1:1
, and
τ
= 1.57x10
-6
×
2(MFD + 2).
10
PLL is operating in 1:1 PLL mode.
11
Jitter is the average deviation from the programmed frequency measured over the specified interval at
maximum f
sys/2
. Measurements are made with the device powered by filtered supplies and clocked by a
stable external clock signal. Noise injected into the PLL circuitry via V
DDSYN
and V
SSSYN
and variation in
crystal oscillator frequency increase the Cjitter percentage for a given interval.
12
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of
Cjitter+Cmod.
13
Modulation percentage applies over an interval of 10
μ
s, or equivalently the modulation rate is 100KHz.
14
Modulation rate selected must not result in f
sys/2
value greater than the f
sys/2
maximum specified value.
Modulation range determined by hardware design.
15
f
sys/2
= f
ico
/ (2
*
2
RFD
)
8
9
Table 11. Processor Bus Input Timing Specifications
Name
Characteristic
1
1
Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line
environment..
TEA and TA pins are being referred to as control inputs.
Refer to figure A-19.
Symbol
Min
Max
Unit
freq
System bus frequency
f
sys/2
50
75
MHz
B0
CLKOUT period
t
cyc
—
1/75
ns
Control Inputs
B1a
Control input valid to CLKOUT high
2
2
3
t
CVCH
9
—
ns
B1b
BKPT valid to CLKOUT high
3
t
BKVCH
9
—
ns
B2a
CLKOUT high to control inputs invalid
2
t
CHCII
0
—
ns
B2b
CLKOUT high to asynchronous control input BKPT invalid
3
t
BKNCH
0
—
ns
Data Inputs
B4
Data input (D[31:0]) valid to CLKOUT high
t
DIVCH
4
—
ns
B5
CLKOUT high to data input (D[31:0]) invalid
t
CHDII
0
—
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| MCF5232CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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