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Electrical Characteristics
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
37
Table 29 lists specifications for the I2C output timing parameters shown in Figure 24.
Figure 24 shows timing for the values in Table 29 and Table 28.
Figure 24. I2C Input/Output Timings
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)
鈥�
1
ms
I6
Clock high time
4
鈥�
tcyc
I7
Data setup time
0
鈥�
ns
I8
Start condition setup time (for repeated start condition only)
2
鈥�
tcyc
I9
Stop condition setup time
2
鈥�
tcyc
Table 29. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Unit
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C interface is designed
to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 29
are minimum values.
Start condition hold time
6
鈥�
tcyc
I21
Clock low period
10
鈥�
tcyc
I32
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
鈥�
s
I41
Data hold time
7
鈥�
tcyc
I53
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
鈥�
3
ns
I61
Clock high time
10
鈥�
tcyc
I71
Data setup time
2
鈥�
tcyc
I81
Start condition setup time (for repeated start condition only)
20
鈥�
tcyc
I91
Stop condition setup time
10
鈥�
tcyc
Table 28. I2C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Unit
I2
I6
I1
I4
I8
I9
I5
I3
I2C_SCL
I2C_SDA
I7
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