參數(shù)資料
型號(hào): MCF52234CAL60
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 31/55頁(yè)
文件大?。?/td> 0K
描述: IC MCU 256K FLASH 60MHZ 112-LQFP
標(biāo)準(zhǔn)包裝: 60
系列: MCF5223x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 60MHz
連通性: CAN,以太網(wǎng),I²C,SPI,UART/USART
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 73
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 112-LQFP
包裝: 托盤(pán)
Electrical Characteristics
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
Freescale Semiconductor
37
Figure 8 shows timing for the values in Table 28 and Table 29.
Figure 8. I2C Input/Output Timings
Table 29. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1 1
Start condition hold time
6
t
CYC
—ns
I2 1
Clock low period
10
t
CYC
—ns
I3 2
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
I4 1
Data hold time
7
t
CYC
—ns
I5 3
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
I6 1
Clock high time
10
t
CYC
—ns
I7 1
Data setup time
2
t
CYC
—ns
I8 1
Start condition setup time (for repeated start
condition only)
20 x tCYC
—ns
I9 1
Stop condition setup time
10 x tCYC
—ns
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 29. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 29 are minimum values.
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
3 Specified at a nominal 50-pF load.
I2
I6
I1
I4
I7
I8
I9
I5
I3
SCL
SDA
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