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參數(shù)資料
型號(hào): MCF52213CAE50
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 30/56頁(yè)
文件大小: 0K
描述: IC MCU 32BIT 128K FLASH 64-LQFP
標(biāo)準(zhǔn)包裝: 160
系列: MCF5221x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: DMA,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: M52210DEMO-ND - BOARD DEV MCF5221X LOW COST
Electrical Characteristics
MCF52211 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
36
2.12
I2C Input/Output Timing Specifications
Table 32 lists specifications for the I2C input timing parameters shown in Figure 7.
Table 33 lists specifications for the I2C output timing parameters shown in Figure 7.
Table 32. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
11
Start condition hold time
2
t
CYC
—ns
I2
Clock low period
8
t
CYC
—ns
I3
SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
1
ms
I6
Clock high time
4
t
CYC
—ns
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
t
CYC
—ns
I9
Stop condition setup time
2
t
CYC
—ns
Table 33. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
111
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 33. The I2C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table 33 are minimum values.
Start condition hold time
6
t
CYC
—ns
Clock low period
10
t
CYC
—ns
I32
2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
——
s
Data hold time
7
t
CYC
—ns
I53
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
—3
ns
Clock high time
10
t
CYC
—ns
Data setup time
2
t
CYC
—ns
Start condition setup time (for repeated start
condition only)
20
t
CYC
—ns
Stop condition setup time
10
t
CYC
—ns
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