參數(shù)資料
型號(hào): MCF5211LCEP66
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: ColdFire Microcontroller
中文描述: ColdFire微控制器
文件頁(yè)數(shù): 35/56頁(yè)
文件大?。?/td> 608K
代理商: MCF5211LCEP66
Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
35
2.10
Table 30
lists specifications for the I
2
C input timing parameters shown in
Figure 7
.
Table 30. I
2
C Input Timing Specifications between I2C_SCL and I2C_SDA
I
2
C Input/Output Timing Specifications
Table 31
lists specifications for the I
2
C output timing parameters shown in
Figure 7
.
Table 31. I
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
11
Start condition hold time
2
×
t
CYC
8
×
t
CYC
ns
I2
Clock low period
ns
I3
SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V)
1
ms
I6
Clock high time
4
×
t
CYC
ns
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
×
t
CYC
2
×
t
CYC
ns
I9
Stop condition setup time
ns
Num
Characteristic
Min
Max
Units
11
1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 31
. The I
2
C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in
Table 31
are minimum values.
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
3
Specified at a nominal 50-pF load.
Start condition hold time
6
×
t
CYC
10
×
t
CYC
ns
I2
1
Clock low period
ns
I3
2
I2C_SCL/I2C_SDA rise time
(V
IL
= 0.5 V to V
IH
= 2.4 V)
μs
I4
1
Data hold time
7
×
t
CYC
ns
I5
3
I2C_SCL/I2C_SDA fall time
(V
IH
= 2.4 V to V
IL
= 0.5 V)
3
ns
I6
1
Clock high time
10
×
t
CYC
2
×
t
CYC
20
×
t
CYC
ns
I7
1
Data setup time
ns
I8
1
Start condition setup time (for repeated start
condition only)
ns
I9
1
Stop condition setup time
10
×
t
CYC
ns
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