參數(shù)資料
型號(hào): MCF5211
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: ColdFire Microcontroller
中文描述: ColdFire微控制器
文件頁數(shù): 37/56頁
文件大?。?/td> 608K
代理商: MCF5211
Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
37
2.12
Equivalent Circuit for ADC Inputs
Figure 10-17 shows the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3
is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and hold circuit moves to (V
REFH
-V
REFL
)/2, while
the other charges to the analog input voltage. When the switches are flipped, the charge on C1 and C2 are averaged via S3, with
the result that a single-ended analog input is switched to a differential voltage centered about (V
REFH
-V
REFL
)/2. The switches
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). There are additional
capacitances associated with the analog input pad, routing, etc., but these do not filter into the S/H output voltage, as S1 provides
isolation during the charge-sharing phase. One aspect of this circuit is that there is an on-going input current, which is a function
of the analog input voltage, V
REF
and the ADC clock frequency.
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100
Ω
s
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
Equivalent input impedance, when the input is selected =
(ADC Clock Rate)
×
(1.4
×
10
-12
)
5.
Figure 8. Equivalent Circuit for A/D Loading
THD
Total harmonic distortion
75
dB
SFDR
Spurious free dynamic range
67 to 70.3
dB
SINAD
Signal-to-noise plus distortion
61 to 63.9
dB
ENOB
Effective number of bits
9.1
10.6
Bits
1
All measurements are preliminary pending full characterization, and made at V
DD
= 3.3V, V
REFH
= 3.3V, and V
REFL
= ground
2
INL measured from V
IN
= V
REFL
to V
IN
= V
REFH
3
LSB = Least Significant Bit
4
INL measured from V
IN
= 0.1V
REFH
to V
IN
= 0.9V
REFH
5
Includes power-up of ADC and V
REF
6
ADC clock cycles
7
Current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC
Table 32. ADC Parameters
1
(continued)
Name
Characteristic
Min
Typical
Max
Unit
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(V
REFH
- V
REFL
)/ 2
125W ESD Resistor
8pF noise damping capacitor
1
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