參數(shù)資料
型號(hào): MCF5208CVM166
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁(yè)數(shù): 27/46頁(yè)
文件大?。?/td> 936K
代理商: MCF5208CVM166
Preliminary Electrical Characteristics
MCF5208 ColdFire
Microprocessor Data Sheet, Rev. 0.5
Preliminary
Freescale Semiconductor
27
Figure 15. Flexbus Write Timing
5.7
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports
either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable
for either Class I or Class II drive strength.
5.7.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data will be latched or driven onto the external bus, relative
to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read
cycles. The SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to
support DDR, a DQS pulse must still be supplied to the device for each data beat of an SDR read. The
ColdFire processor accomplishes this by asserting a signal called SD_DQS during read cycles. Care must
be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS
signal and its usage.
FB_CLK
A[23:0]
D[31:0]
R/W
TS
FB_CS
n
, BE/BWE
n
TA
FB1
FB2
FB9
FB3
FB6
FB7
OE
FB8
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