
Table 24. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
Min.
Max.
Unit
Notes
DNL
Differential non-
linearity
12 bit modes
<12 bit modes
±0.7
±0.2
±TBD
±0.5
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
INL
Integral non-
linearity
12 bit modes
<12 bit modes
±0.5
±TBD
Max
averaging
EFS
Full-scale error
12 bit modes
<12 bit modes
±0.4
VADIN =
VDDA
EQ
Quantization
error
12 bit modes
—
±0.5
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
–40°C to 105°C
—
TBD
—
mV/°C
VTEMP25
Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
Figure TBD
Figure 10. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
Analog
MCF51JF128 Advance Information Data Sheet, Rev. 3, 08/2011.
Freescale Semiconductor, Inc.
Preliminary
37