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| 型號(hào)： | MC9SDG128BCFUR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, 2.20 MM HEIGHT, 0.65 MM PITCH, QFP-80 |
| 文件頁數(shù)： | 117/128頁 |
| 文件大?。?/td> | 2002K |
| 代理商： | MC9SDG128BCFUR2 |
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MC9S12DT128B Device User Guide — V01.09
87
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
Table A-1 Absolute Maximum Ratings1
NOTES:
1. Beyond absolute maximum ratings device might be damaged.
Num
Rating
Symbol
Min
Max
Unit
1
I/O, Regulator and Analog Supply Voltage
VDD5
-0.3
6.0
V
2
Digital Logic Supply Voltage 2
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
VDD
-0.3
3.0
V
3
PLL Supply Voltage 2
VDDPLL
-0.3
3.0
V
4
Voltage difference VDDX to VDDR and VDDA
VDDX
-0.3
0.3
V
5
Voltage difference VSSX to VSSR and VSSA
VSSX
-0.3
0.3
V
6
Digital I/O Input Voltage
VIN
-0.3
6.0
V
7
Analog Reference
VRH, VRL
-0.3
6.0
V
8
XFC, EXTAL, XTAL inputs
VILV
-0.3
3.0
V
9
TEST input
VTEST
-0.3
10.0
V
10
Instantaneous Maximum Current
Single pin limit for all digital I/O pins 3
3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
I
D
-25
+25
mA
11
Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL4
4. Those pins are internally clamped to VSSPLL and VDDPLL.
I
DL
-25
+25
mA
12
Instantaneous Maximum Current
Single pin limit for TEST 5
5. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
I
DT
-0.25
0
mA
13
Storage Temperature Range
T
stg
– 65
155
°C
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