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| 型號： | MC9S12XF512J0CLMR |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, QFP112 |
| 封裝： | LQFP-112 |
| 文件頁數(shù)： | 1142/1306頁 |
| 文件大小： | 8007K |
| 代理商： | MC9S12XF512J0CLMR |
Chapter 19 Port Integration Module (S12XFPIMV2)
MC9S12XF - Family Reference Manual, Rev.1.19
850
Freescale Semiconductor
19.3.5
Port A Data Direction Register (DDRA)
19.3.6
Port B Data Direction Register (DDRB)
Address 0x0002 (PRR)
Access: User read/write(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
Reset
00000000
Figure 19-3. Port A Data Direction Register (DDRA)
Table 19-6. DDRA Register Field Descriptions
Field
Description
7-0
DDRA
Port A Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits
will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is congured as output.
0 Associated pin is congured as high-impedance input.
Address 0x0003 (PRR)
Access: User read/write(1)
1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
Reset
00000000
Figure 19-4. Port B Data Direction Register (DDRB)
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