
Chapter 27 512 KByte Flash Module (S12XFTM512K3V1)
MC9S12XE-Family Reference Manual , Rev. 1.13
1086
Freescale Semiconductor
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 27-7. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
6–0
FDIV[6:0]
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz (range from 800 kHz – 1.05 MHz) for use by the Flash module to
control timed events during program and erase algorithms.
Table 27-8 shows recommended values for FDIV[6:0]
information.