
Chapter 7 Background Debug Module (S12XBDMV2)
MC9S12XE-Family Reference Manual Rev. 1.13
Freescale Semiconductor
285
7.3.2.2
BDM CCR LOW Holding Register (BDMCCRL)
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCRL register
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCRL register in this CPU mode. Out of reset in all other modes the
BDMCCRL register is read zero.
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM rmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
Table 7-3. BDM Clock Sources
PLLSEL
CLKSW
BDMCLK
0
Bus clock dependent on oscillator
0
1
Bus clock dependent on oscillator
1
0
Alternate clock (refer to the device specication to determine the alternate clock source)
1
Bus clock dependent on the PLL
Register Global Address 0x7FFF06
7
6
5
4
3
2
1
0
R
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
W
Reset
Special Single-Chip Mode
1
0
1
0
All Other Modes
0