Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
557
14.3.2.23 Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
All bits reset to zero.
14.3.2.24 Input Control System Control Register (ICSYS)
Read: Anytime
Write: Once in normal modes
00000111
32 bus clock cycles
00001111
64 bus clock cycles
00011111
128 bus clock cycles
00111111
256 bus clock cycles
01111111
512 bus clock cycles
11111111
1024 bus clock cycles
Module Base + 0x002A
76543210
R
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
W
Reset
00000000
Figure 14-46. Input Control Overwrite Register (ICOVW)
Table 14-30. ICOVW Field Descriptions
Field
Description
7:0
NOVW[7:0]
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
or latch occurs.
1 The related capture register or holding register cannot be written by an event unless they are empty (see
latched in the holding register.
Module Base + 0x002B
76543210
R
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
W
Reset
00000000
Figure 14-47. Input Control System Register (ICSYS)
Table 14-29. Delay Counter Select Examples when PRNT = 1
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
Delay
