
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
338
Freescale Semiconductor
7.3.2.20
16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write only used in the ag clearing mechanism for bit 7. Writing a one to bit 7 clears the ag. Writing a
zero will not affect the current status of the bit.
NOTE
When TFFCA = 1, the ag cannot be cleared via the normal ag clearing
All bits reset to zero.
Table 7-23. Modulus Counter Prescaler Select
MCPR1
MCPR0
Prescaler Division
00
1
01
4
10
8
11
16
76543210
R
MCZF
0
POLF3
POLF2
POLF1
POLF0
W
Reset
00000000
= Unimplemented or Reserved
Figure 7-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Table 7-24. MCFLG Field Descriptions
Field
Description
7
MCZF
Modulus Counter Underow Flag — The ag is set when the modulus down-counter reaches 0x0000.
The ag indicates when interrupt conditions have occurred. The ag can be cleared via the normal ag clearing
mechanism (writing a one to the ag) or via the fast ag clearing mechanism (Reference TFFCA bit in
3:0
POLF[3:0]
First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the rst edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The rst input capture has been caused by a falling edge.
1 The rst input capture has been caused by a rising edge.