
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
541
Chapter 13
Periodic Interrupt Timer (S12PIT24B4CV1)
13.1
Introduction
The period interrupt timer (PIT) is an array of 24-bit timers that can be used to trigger peripheral modules
or raise periodic interrupts. Refer to
Figure 13-1 for a simplied block diagram.
13.1.1
Glossary
13.1.2
Features
The PIT includes these features:
Four timers implemented as modulus down-counters with independent time-out periods.
Time-out periods selectable between 1 and 224 bus clock cycles. Time-out equals m*n bus clock
cycles with 1 <= m <= 256 and 1 <= n <= 65536.
Timers that can be enabled individually.
Four time-out interrupts.
Four time-out trigger output signals available to trigger peripheral modules.
Start of timer channels can be aligned to each other.
13.1.3
Modes of Operation
Refer to the SoC guide for a detailed explanation of the chip modes.
Run mode
This is the basic mode of operation.
Wait mode
Acronyms and Abbreviations
PIT
Periodic Interrupt Timer
ISR
Interrupt Service Routine
CCR
Condition Code Register
SoC
System on Chip
micro time bases
clock periods of the 16-bit timer modulus down-counters, which are generated by the 8-bit
modulus down-counters.