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S12S Debug (S12SDBG) Module
S12P-Family Reference Manual, Rev. 1.07
Freescale Semiconductor
PRELIMINARY
151
Field3 Bits in Compressed Pure PC Modes
Each time that PC[17:6] differs form the previous base PC[17:6], then a new base address is stored. The
base address zero value is the lowest address in the 64 address range
The rst line of the trace buffer always gets a base PC address, this applies also on rollover.
6.4.5.5
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read provided the DBG module is not armed, is congured for
tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer
is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word
write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out rst-in rst-out. By reading CNT in DBGCNT the number of
valid lines can be determined. DBGCNT does not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with
the oldest data entry may also contain newer data entries in elds 0 and 1. Thus if rollover is indicated by
the TBF bit, the line status must be decoded using the INF bits in eld3 of that line. If both INF bits are
clear then the line contains only entires from before the last rollover.
If INF0=1 then eld 0 contains post rollover data but elds 1 and 2 contain pre rollover data.
If INF1=1 then elds 0 and 1 contain post rollover data but eld 2 contains pre rollover data.
The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables
an interrupted trace buffer read sequence to be easily restarted from the oldest data entry.
The least signicant word of line is read out rst. This corresponds to the elds 1 and 0 of
Table 6-36. The
next word read returns eld 2 in the least signicant bits [3:0] and “0” for bits [15:4].
Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM
pointer occurs.
6.4.5.6
Trace Buffer Reset State
The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system
reset occur, the trace session information from immediately before the reset occurred can be read out and
the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current
Table 6-40. Compressed Pure PC Mode Field 3 Information Bit Encoding
INF1
INF0
TRACE BUFFER ROW CONTENT
0
Base PC address TB[17:0] contains a full PC[17:0] value
0
1
Trace Buffer[5:0] contain incremental PC relative to base address zero value
1
0
Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value
1
Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value