
Chapter 14 Timer Module (TIM16B8CV1) Block Description
MC9S12KT256 Data Sheet, Rev. 1.16
470
Freescale Semiconductor
14.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
14.3.2.11 Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
Module Base + 0x000C
76543210
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
00000
Figure 14-18. Timer Interrupt Enable Register (TIE)
Table 14-14. TIE Field Descriptions
Field
Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding ag is disabled from causing a hardware interrupt. If set,
the corresponding ag is enabled to cause a interrupt.
Module Base + 0x000D
76543210
R
TOI
000
TCRE
PR2
PR1
PR0
W
Reset
0
00000
= Unimplemented or Reserved
Figure 14-19. Timer System Control Register 2 (TSCR2)