參數(shù)資料
型號： MC9S12DP256CCPV
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： device made up of standard HCS12 blocks and the HCS12 processor core
中文描述： 設(shè)備組成水平的HCS12塊和HCS12的處理器核心
文件頁數(shù)： 107/128頁
文件大小： 2560K
代理商： MC9S12DP256CCPV
107
A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.5.1 Startup
Table A-14
summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
A.5.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the VDD supply. They are also valid
ifthedeviceispoweredexternally.AfterreleasingthePORresettheoscillatorandtheclockqualitycheck
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
codewhenVDD5isoutofspecificationlimits,theSRAMcontentsintegrityisguaranteedifafterthereset
the PORF bit in the CRG Flags Register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
Table A-14 Startup Characteristics
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T POR release level
V
PORR
2.07
V
2
T POR assert level
V
PORA
0.97
V
3
D Reset input pulse width, minimum input time
PW
RSTL
2
t
osc
4
D Startup from Reset
n
RST
192
196
n
osc
5
D Interrupt pulse width, IRQ edge-sensitive mode
PW
IRQ
20
ns
6
D Wait recovery startup time
t
WRS
14
t
cyc
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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