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參數(shù)資料
| 型號： | MC9S12DG256VPVE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 256K FLASH 25MHZ 112-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | HCS12 |
| 核心處理器： | HCS12 |
| 芯體尺寸： | 16-位 |
| 速度： | 25MHz |
| 連通性： | CAN，I²C，SCI，SPI |
| 外圍設(shè)備： | PWM，WDT |
| 輸入/輸出數(shù)： | 91 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 12K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.35 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 112-LQFP |
| 包裝： | 托盤 |
MC9S12D-FamilyPP
Rev 6.1, 23-Oct-02
MC9S12D-Family
Product Brief
16-Bit Microcontroller
Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flash-
based microcontrollers are fully pin compatible and enable users to choose between different memory
and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard
on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash
EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications
interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two
8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM),
J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System
resource mapping, clock generation, interrupt control and bus interfacing are managed by the system
integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the
external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for
lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be
adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22
I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode.
Features
NOTE
Not all features listed here are available in all configurations.
Additional information about D and B family inter-operability is given in:
EB386 “HCS12 D-Family Compatibility Considerations” and
EB388 “Using the HCS12 D-Family as a development platform for the HCS12 B family”
16-bit CPU12
— Upward compatible with M68HC11 instruction set
— Interrupt stacking and programmer’s model identical to M68HC11
— HCS12 Instruction queue
— Enhanced indexed addressing
Multiplexed bus
— Single chip or expanded
— 16 address/16 data wide or 16 address/8 data narrow modes
— External address space 1MByte for Data and Program space (112 pin package only)
Wake-up interrupt inputs depending on the package option
— 8-bit port H
— 2-bit port J1:0
— 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module
— 8-bit port P shared with PWM or SPI1,2
Memory options
— 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM
— 1K, 2K, 4K Byte EEPROM
— 2K, 4K, 8K, 12K, 14K Byte RAM
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