Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
325
Rev 01.24
10.4.2.1
Message Transmit Background
Modern application layer software is built upon two fundamental assumptions:
Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus
between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the
previous message and only release the CAN bus in case of lost arbitration.
The internal message queue within any CAN node is organized such that the highest priority
message is sent out rst, if more than one message is ready to be sent.
The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer
must be reloaded immediately after the previous message is sent. This loading process lasts a nite amount
of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted
stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts
with short latencies to the transmit interrupt.
A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending
and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a
message is nished while the CPU re-loads the second buffer. No buffer would then be ready for
transmission, and the CAN bus would be released.
At least three transmit buffers are required to meet the rst of the above requirements under all
circumstances. The MSCAN has three transmit buffers.
The second requirement calls for some sort of internal prioritization which the MSCAN implements with
10.4.2.2
Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple
messages to be set up in advance. The three buffers are arranged as shown in
Figure 10-38.All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see
To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set
(CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the
(CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see
CANTBSEL register simplies the transmit buffer selection. In addition, this scheme makes the handler
software simpler because only one address area is applicable for the transmit process, and the required
address space is minimized.
The CPU then stores the identier, the control bits, and the data content into one of the transmit buffers.
Finally, the buffer is agged as ready for transmission by clearing the associated TXE ag.