參數(shù)資料
型號: MC9S08RD60DWE
廠商: Freescale Semiconductor
文件頁數(shù): 225/234頁
文件大?。?/td> 0K
描述: IC MCU 60K FLASH 2K RAM 28-SOIC
標準包裝: 26
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 8MHz
連通性: SCI
外圍設備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 60KB(60K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Central Processor Unit (S08CPUV2)Central Processor Unit (S08CPUV2)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
90
Freescale Semiconductor
7.3
Addressing Modes
Addressing modes dene the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
Table 7-1. CCR Register Field Descriptions
Field
Description
7
V
Two’s Complement Overow Flag — The CPU sets the overow ag when a two’s complement overow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overow ag.
0 No overow
1 Overow
4
H
Half-Carry Flag — The CPU sets the half-carry ag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry ag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the rst instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative ag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most signicant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
1
Z
Zero Flag — The CPU sets the zero ag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1 Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow ag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow ag.
0 No carry out of bit 7
1 Carry out of bit 7
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