
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor
149
9.4.2
LCDRAM Registers
For a segment on the LCD panel to be displayed, data must be written to the LCDRAM registers. Each bit
in the LCDRAM registers correspond to a segment on the LCD panel.
The LCDRAM registers provide access to two different register groups depending on the state of the
LCDDRMS bit in the LCDCMD register. If LCDDRMS = 0, the LCDRAM register accesses a register
bank that controls the on/off state for frontplane drivers. If LCDDRMS = 1, the LCDRAM register bank
accesses a register bank that enables the blink mode for each individual LCD segment.
If LCDDRMS = 0, when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set, writing a 1 to
a given LCDRAM location will result in the corresponding display segment being driven with a
differential root mean square (RMS) voltage necessary to turn the segment on.Writing a 0 to a given
location will result in the corresponding display segment being driven with a differential RMS voltage
necessary to turn the segment off.
The LCDRAM is a dual port RAM that interfaces with the internal address and data buses of the MCU.
When LCDEN = 0, the LCDRAM registers can be used as on-chip RAM. Writing or reading of the
LCDEN bit does not change the contents of the LCDRAM registers.After a reset, the LCDRAM contents
will be indeterminate.
9.4.2.1
LCDRAM Data Clear Command
The LCD module data register clear command deasserts all accessible bits in the LCDRAM registers.
LCDDRMS bit in the LCDCMD register determines which LCDRAM registers bits are accessible.To
clear all LCD segment blink enables in the LCDRAM registers, the LCDCLR bit must be asserted only
when the LCDDRMS bit is asserted. To clear the entire LCD display, the LCDCLR bit must be asserted
only when the LCDDRMS bit is deasserted.
9.4.2.2
LCDRAM Data Blank Command
The LCD module display blank command clears all segments in the LCD display regardless of the contents
of the LCDRAM registers or the state of the LCDDRMS bit. This bit does not disable the LCD module
timing generator. Writing or reading of the BLANK bit does not change the contents of the LCDRAM
registers.
9.4.3
LCD Blinking
The LCD module LCD panel blink capabilities are very flexible. The LCD module can be congured to
blink either individual LCD segments or the entire LCD panel. The blink rate frequency is congured
using the BRATE[2:0] bit eld.
The LCD will blink at the congured frequency while the BLINK bit in the LCDBCTL register is set to 1.
When the BLINK bit is modied to start or stop the LCD display blinking, the BLINK command change
takes place at the beginning of the next LCD frame cycle.