Chapter 16 Timer/PWM Module (S08TPMV3)
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
331
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register)
such that the buffer latches remain in the state they were in when the BDM became active, even if one or
both halves of the modulo register are written while BDM is active. Any write to the modulo registers
bypasses the buffer latches and directly writes to the modulo register while BDM is active.
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the rst
counter overow will occur.
16.3.4
TPM Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel-interrupt-status ag and control bits used to congure the interrupt
enable, channel conguration, and pin function.
76543210
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
00000000
Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)
76543210
R
Bit 7
654321
Bit 0
W
Reset
00000000
Figure 16-11. TPM Counter Modulo Register Low (TPMxMODL)
76543210
R
CHnF
CHnIE
MSnB
MSnA
ELSnB
ELSnA
00
W0
Reset
00000000
= Unimplemented or Reserved
Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)