
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
MC9S08DV60 Series Data Sheet, Rev 3
Freescale Semiconductor
245
12.4.3
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Table 12-30. IDR1 Register Field Descriptions
Field
Description
7:5
ID[2:0]
Standard Format Identier — The identiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the
most signicant bit and is transmitted rst on the CAN bus during the arbitration procedure. The priority of an
identier is dened to be highest for the smallest binary number. See also ID bits in
Table 12-29.4
RTR
Remote Transmission Request — This ag reects the status of the Remote Transmission Request bit in the
CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the
transmission of an answering frame in software. In the case of a transmit buffer, this ag denes the setting of
the RTR bit to be sent.
0 Data frame
1 Remote frame
3
IDE
ID Extended — This ag indicates whether the extended or standard identier format is applied in this buffer. In
the case of a receive buffer, the ag is set as received and indicates to the CPU how to process the buffer
identier registers. In the case of a transmit buffer, the ag indicates to the MSCAN what type of identier to send.
0 Standard format (11 bit)
1 Extended format (29 bit)
76543210
R
W
Reset:
xxxxxxxx
= Unused; always read ‘x’
Figure 12-31. Identier Register 2 — Standard Mapping
76543210
R
W
Reset:
xxxxxxxx
= Unused; always read ‘x’
Figure 12-32. Identier Register 3 — Standard Mapping