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參數(shù)資料
| 型號： | MC9S08DV32CLH |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 82/414頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32K FLASH 2K RAM 64-LQFP |
| 標準包裝： | 160 |
| 系列： | S08 |
| 核心處理器： | S08 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，I²C，LIN，SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 53 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
MC9S08DV60 Series Data Sheet, Rev 3
172
Freescale Semiconductor
10.1.3
Alternate Clock
The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided
by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The
alternate clock for the MC9S08DV60 Series MCU devices is the external reference clock (MCGERCLK).
The selected clock source must run at a frequency such that the ADC conversion clock (ADCK) runs at a
frequency within its specied range (fADCK) after being divided down from the ALTCLK input as
determined by the ADIV bits.
ALTCLK is active while the MCU is in wait mode provided the conditions described above are met. This
allows ALTCLK to be used as the conversion clock source for the ADC while the MCU is in wait mode.
ALTCLK cannot be used as the ADC conversion clock source while the MCU is in either stop2 or stop3.
10.1.4
Hardware Trigger
The ADC hardware trigger, ADHWT, is the output from the real time counter (RTC). The RTC counter
can be clocked by either MCGERCLK or a nominal 1 kHz clock source.
The period of the RTC is determined by the input clock frequency, the RTCPS bits, and the RTCMOD
register. When the ADC hardware trigger is enabled, a conversion is initiated upon an RTC counter
overow.
The RTC can be congured to cause a hardware trigger in MCU run, wait, and stop3.
Table 10-1. ADC Channel Assignment
Notes:
1 For information, see Section 10.1.5, “Temperature Sensor”.
ADCH
Channel
Input
00000
AD0
PTA0/ADP0/MCLK
00001
AD1
PTA1/ADP1/ACMP1+
00010
AD2
PTA2/ADP2/ACMP1P-
00011
AD3
PTA3/ADP3/ACMP1O
00100
AD4
PTA4/ADP4
00101
AD5
PTA5/ADP5
00110
AD6
PTA6/ADP6
00111
AD7
PTA7/ADP7
01000
AD8
PTB0/ADP8
01001
AD9
PTB1/ADP9
01010
AD10
PTB2/ADP10
01011
AD11
PTB3/ADP11
01100
AD12
PTB4/ADP12
01101
AD13
PTB5/ADP13
01110
AD14
PTB6/ADP14
01111
AD15
PTB7/ADP15
10000–
AD16 through AD25
Reserved
11001
11010
AD26
Temperature Sensor1
11011
AD27
Internal Bandgap2
11100
Reserved
11101
VREFH
11110
VREFL
11111
Module Disabled
None
ADCH
Channel
Input
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