- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359729 > MC9328MX21DVH (Motorola, Inc.) i.MX family of microprocessors PDF資料下載
參數(shù)資料
| 型號： | MC9328MX21DVH |
| 廠商： | Motorola, Inc. |
| 英文描述： | i.MX family of microprocessors |
| 中文描述： | i.MX系列微處理器 |
| 文件頁數(shù)： | 74/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC9328MX21DVH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當(dāng)前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
MC9328MX1 Advance Information, Rev. 4
74
Freescale Semiconductor
Specifications
3.18 SDRAM Memory Controller
A write to an address within the memory region initiates the program sequence. The first command issued to the
SyncFlash is Load Command Register. A [7:0] determine which operation the command performs. For this write
setup operation, an address of 0x40 is hardware generated. The bank and other address lines are driven with the
address to be programmed. The next command is Active which registers the row address and confirms the bank
address. The third command supplies the column address, re-confirms the bank address, and supplies the data to be
written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required.
A read to the memory region initiates the status read sequence. The first command issued to the SyncFlash is the
Load Command Register with A [7:0] set to 0x70 which corresponds to the Read Status Register operation. The
bank and other address lines are driven to the selected address. The second command is Active which sets up the
status register read. The bank and row addresses are driven during this command. The third command of the triplet
is Read. Bank and column addresses are driven on the address bus during this command. Data is returned from
memory on the low order 8 data bits following the CAS latency.
3a
Clock fall time
1
–
5
–
5/10
ns
3b
Clock rise time
1
–
6.67
–
5/10
ns
4a
Output delay time
1
5.7
–
5
–
ns
4b
Output setup time
1
5.7
–
5
–
ns
1.
C
L
of PWMO = 30 pF
Table 33. PWM Output Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9328MX21DVK | i.MX family of microprocessors |
| MC9328MX21DVM | i.MX family of microprocessors |
| MC9328MX21VG | i.MX family of microprocessors |
| MC9328MX21VH | i.MX family of microprocessors |
| MC9328MX21VK | i.MX family of microprocessors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21DVK | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVM | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVMR2 | 功能描述:處理器 - 專門應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。