參數(shù)資料
型號： MC9328MX1DVM15R2
廠商： Freescale Semiconductor
文件頁數(shù)： 62/100頁
文件大?。?/td> 0K
描述： IC MCU I.MX 150MHZ 256-MAPBGA
標準包裝： 1,000
系列： i.MX1
核心處理器： ARM9
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB
外圍設備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 110
程序存儲器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.7 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -30°C ~ 70°C
封裝/外殼： 256-MAPBGA
包裝： 帶卷 (TR)
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
64
Freescale Semiconductor
Figure 38. SPI Interface Timing Diagram Using MC13180
4.8
SPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the SPI 1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI1 Sample Period Control Register (PERIODREG1) and the SPI2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either SPI 1 or
SPI 2. When the SPI 1 module is configured as a slave, the user can configure the SPI1 Control Register
(CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input
signal, and is used to latch data into or load data out to the internal data shift registers, as well as to
increment the data FIFO. Figure 39 through Figure 43 show the timing relationship of the master SPI using
different triggering mechanisms.
Table 23. SPI Interface Timing Parameter Table Using MC13180
Ref No.
Parameter
Minimum
Maximum
Unit
1
SPI_EN setup time relative to rising edge of SPI_CLK
15
–
ns
2
Transmit data delay time relative to rising edge of SPI_CLK
0
15
ns
3
Transmit data hold time relative to rising edge of SPI_EN
0
15
ns
4
SPI_CLK rise time
0
25
ns
5
SPI_CLK fall time
0
25
ns
6
SPI_EN hold time relative to falling edge of SPI_CLK
15
–
ns
7
Receive data setup time relative to falling edge of SPI_CLK1
1 The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by programming
SPI_Control (0x00216138) register together with system clock.
15
–
ns
8
Receive data hold time relative to falling edge of SPI_CLK1
15
–
ns
9
SPI_CLK frequency, 50% duty cycle required1
–20
MHz
SPI_EN (BT11)
SPI_DATA_OUT (BT12)
SPI CLK (BT13)
SPI_DATA_IN (BT4)
1
7
4
5
8
2
3
6
9
相關PDF資料
PDF描述
MC912D60CCPVE IC MCU 16BIT 112-LQFP
MCF5280CVM66J IC MPU RISC 66MHZ 256-MAPBGA
VI-23T-CU CONVERTER MOD DC/DC 6.5V 200W
VE-23X-CU CONVERTER MOD DC/DC 5.2V 200W
VE-23W-CU CONVERTER MOD DC/DC 5.5V 200W
相關代理商/技術參數(shù)
參數(shù)描述
MC9328MX1DVM20 功能描述:處理器 - 專門應用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據緩存: 數(shù)據 RAM 大小:128 KB 數(shù)據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX1DVM20R2 功能描述:處理器 - 專門應用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據緩存: 數(shù)據 RAM 大小:128 KB 數(shù)據 ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX1P/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
MC9328MX1S 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
MC9328MX1SRM/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*