參數(shù)資料
型號(hào)： MC92600ZTB
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
封裝： 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, PLASTIC, MABGA-196
文件頁(yè)數(shù)： 29/98頁(yè)
文件大?。?/td> 1018K
代理商： MC92600ZTB
MOTOROLA
Chapter 3. Receiver
3-7
Alignment Modes
3.3.2.1
Word Synchronization Method
Word synchronization aligns characters in the receiver’s alignment FIFO. Synchronization
is accomplished by lining up word synchronization events detected by each of the receivers,
such that all are coincident at the same stage of their FIFO.
A word synchronization event is dened differently depending on the state of the
BSYNC_0 and BSYNC_1 signals. Table 3-3 shows the type of word synchronization event
used.
There are two types of word synchronization events: the 4/1 idle sequence and the
disparity-based idle sequence.
The 4/1 idle sequence is dened as four consecutive idle characters followed by a
non-idle character.
The disparity-based idle sequence is 16 consecutive idle characters with improper
disparity on the second and fourth idle character in the sequence. The
disparity-based idle sequence is described further in Section 2.4.1, “Transmitting
Word synchronization events must be generated at all concerned transmitters
simultaneously in order for synchronization to be achieved. Word synchronization events
must be received at all concerned receivers within 40 bit-times of each other.
Word synchronization events are used to establish a relationship between the received bytes
in each of the receivers. The bytes of a word are matched and presented simultaneously at
the receiver interface. Once synchronization is achieved, the receiver tolerates +/- 6
bit-times of drift between receivers. If drift exceeds +/- 6 bit-times, the receiver will
continue to operate. However, the received bytes will no longer be synchronized properly
because the receiver remains locked onto the initially established synchronization. Word
synchronization remains locked until one of three events occurs that indicate loss of
synchronization.
Word synchronization lock can be lost in three ways:
When one or more of the receivers lose or change byte alignment. Byte alignment
When overrun/underrun is detected on one or more of the receivers but not on all
simultaneously, see Section 3.4.2, “Reference Clock Timing Mode” for more about
overrun/underrun.
Table 3-3. Word Synchronization Events
Word Synchronization Event
BSYNC_0
BSYNC_1
4 idle/1 non-idle
Low
don’t care
Disparity-based idle sequence
High
Low
相關(guān)PDF資料
PDF描述
MC92600JUB SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
MC92602ZTA SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196
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