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參數(shù)資料
| 型號： | MC92460ZU |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC HDLC 40-CH 480-TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 控制器類型： | HDLC 控制器 |
| 接口： | IEEE 1149.1 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 480-LBGA |
| 供應(yīng)商設(shè)備封裝： | 408-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
Common features
> Independent SerDes channels with
full-duplex differential data links
> Configurable as a single channel
device to provide redundant transmit
and receive serial links
> Selectable speed range: 1.25 Gbaud
or 0.625 Gbaud
> Internal 8B/10B encoder/decoders
> Source synchronous parallel data
input interfaces
> Selectable source-synchronous
or source-centered timing on receiver
interface
> Links drive 50-ohm or 75-ohm media
(100- or 150-ohm differential),
backplane or cable
> Link inputs have on-chip receiver
link termination and are “hot-swap”
compatible
> Low power: <0.6 W, under typical
conditions, while operating in backplane
mode with all transceivers at full speed
> Unused transceiver channels may be
individually disabled to reduce power
consumption
> IEEE Std 1149.1 JTAG support and
full-speed built-in self test functions
Backplane application features
> Link-to-link synchronization supports
aligned, multi-channel, word transfers.
Synchronization mechanism tolerates
up to 40 bit-times of link-to-link media
delay skew
> Supports Disparity Based Word Sync
Events for compatibility with legacy
transceivers
> Selectable COMMA code group
alignment mode enables aligned or
unaligned transfers
Ethernet friendly features
> GMII, TBI, RGMII or RTBI data interface
options
> COMMA code group alignment
in receivers
> Provides the PCS and PMA layers
for Ethernet PHYs as specified in
IEEE Std. 802.3-2002
> MDIO slave interface and registers
as defined in IEEE Std. 802.3-2002
is fully supported
> MDIO interface is available in
all operating modes
Technical specifications
> All channels have:
8B/10B encoder/decoder that can
be enabled or bypassed in Ten-Bit
Interface (TBI) mode
Clock generation/recovery
Independent 8/10-bit or 4/5-bit system
I/F with parallel-to-serial, serial-to-parallel
conversion
> Transmit data clock is selectable between
per-channel transmit clock or channel ‘A’
transmit clock
> Received data may be clocked at
the recovered clock or the reference
clock frequencies
> Half frequency, split-phase recovered clock
in TBI (10-bit) mode
> Transceiver Links operate over 50-ohm or
75-ohm media (100- or 150-ohm differential)
for lengths of up to 1.5 meters of FR-4
board/back-plane, or 10 meters of coax
> No external loop filter components required
> System BIST test modes with error counter
> Loopback BIST isolated from link inputs
and outputs
> IEEE Std 1149.1 JTAG boundary
scan support
> LVPECL differential reference clock input
with single-ended LVTTL reference clock
input option
> Two single ended buffered Ref Clock outputs
provided for associated logic interfaces
> Frequency offset tolerance between transmitter
and receiver in excess of ± 250 ppm
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
Freescale Semiconductor, Inc. 2004
MC92604FS/D
REV 1
Parametrics
> Power Supply
Core Power Supply: 1.8 V ± 0.15 Vdc
Data I/O Power Supply:
(LVTTL) 3.3 V ± 0.10 Vdc
or (SSTL-2) 2.5 V ± 0.20 Vdc
Link I/O Power Supply:
1.8 V ± 0.15 Vdc
> Power Dissipation
Typical operation at maximum speed:
<250 mW per channel in backplane
mode <350 mW per channel in
Ethernet mode
Package
> 196 pin MAPBGA
(15x15 mm body size,
1.0 mm ball pitch)
Learn More: For more information about Freescale products, visit www.motorola.com/semiconductors
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