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參數(shù)資料
| 型號： | MC92052 |
| 廠商： | Motorola, Inc. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 40K |
| 代理商： | MC92052 |
MC92052
Motorola
3
fication. This block uses RXCLK provided by the ATM
layer. The FIFO is used for rate adaptation between RX-
CLK (the UTOPIA interface clock) and the device clock.
Tx UTOPIA Interface
The Transmit UTOPIA interface accepts ATM cells from
the ATM layer according to the UTOPIA specification.
The cells are stored in the transmit cell FIFO. This block
uses TXCLK provided by the ATM layer. The FIFO is
used for rate adaptation between TXCLK (the UTOPIA
interface clock) and the device clock.
Tx Cell Functions
The transmit cell functions block reads ATM cells from
the transmit cell FIFO. If there are no cells available
when an upstream frame should be transmitted, the cell
functions block generates an idle cell. It calculates the
HEC value based on the ATM header of each cell and
inserts it in the fifth octet of the cell.
A count of the cells transferred from the transmit cell
FIFO is maintained.
Data Link Insertion
The data link insertion block provides direct serial ac-
cess to the data link bytes of the upstream frame head-
ers. The data link stream for the upstream frames is
optionally inserted using an output clock pin and an in-
put data pin.
Frame Header Generation
The frame header generation block generates the six
header bytes for each upstream frame.
Randomizer
The randomizer operates on 4 header bytes and 53
ATM cell bytes of each upstream frame. It is initialized
to all ones at the beginning of each frame. The 2 SYNC
bytes are not randomized.
Reed-Solomon Encoder
The Reed-Solomon encoder operates on 57 bytes of
the upstream frame and adds 8 parity bytes to produce
a (65,57) RS code.
Tx PMD Interface
The transmit PMD interface block transfers bursts of se-
rial data. The control signals of this interface include a
transmit enable signal and a clock signal that is gener-
ated internally by dividing down the clock provided at
the receive PMD interface.
Microprocessor Interface
The microprocessor interface is an 8-bit generic slave
interface. It is used for initializing the internal registers
and reading status registers and counters.
JTAG
The MC92052 provides JTAG boundary scan.
System Functional Description
Downstream Data Flow
In the downstream direction, the MC92052 receives the
data and clock recovered by the PMD device. The
frame alignment is recovered by searching for the
SYNC bytes. Once the frame alignment is known, the
header and payload are split into separate processing
paths. The header undergoes error correction by a
Reed-Solomon decoder. It is then derandomized and
processed in accordance with the definition of the head-
er bytes.
The payload passes through a convolutional deinter-
leaver and is then divided into blocks of 66 bytes. Each
block undergoes error correction by a Reed-Solomon
decoder. The corrected payload data is then derandom-
ized. The resulting data stream is delineated into ATM
cells using the HEC-based delineation method of
ITU-T Recommendation I.432. Any physical layer cells
are discarded, and the remaining cells are transferred to
the ATM layer using a UTOPIA compliant interface.
Upstream Data Flow
In the upstream direction, the MC92052 implements
TDMA, including sign-on, as directed by the network de-
vice using the frame overhead of the downstream
frames. If no cell is available from the ATM layer, an idle
cell is generated. The frame overhead is added to the
ATM cell, and then the 57-byte frame is randomized. A
Reed-Solomon encoder adds eight parity bytes. The
entire frame is transferred to the PMD device along with
an enable signal to provide the proper timing with re-
spect to the downstream superframe.
Other Functions
A microprocessor interface is provided for configura-
tion, control, and status monitoring.
A standard IEEE 1149.1 boundary scan test port is pro-
vided.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC92053 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MC92300 | VITERBI Decoder for Digital TV |
| MC92300CG | VITERBI Decoder for Digital TV |
| MC92305 | 16/32/64/128/256 QAM RECEIVER AND REED-SOLOMON DECODER |
| MC92305CD | 16/32/64/128/256 QAM RECEIVER AND REED-SOLOMON DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC92053 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Quad FTTC Network Framer |
| MC92101CO | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC921G | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC92300 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:VITERBI Decoder for Digital TV |
| MC92300CG | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:VITERBI Decoder for Digital TV |
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