
Enhanced Capture Timer
Technical Data
MC68HC912DT128A — Rev 4.0
266
Enhanced Capture Timer
MOTOROLA
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
The flag is set when the modulus down-counter reaches $0000.
A write one to this bit clears the flag. Write zero has no effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
POLF3 – POLF0 — First Input Capture Polarity Status
This are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
Read or write any time.
MCFLG — 16-Bit Modulus Down-Counter FLAG Register
$00A7
BIT 7
6
5
4
3
2
1
BIT 0
MCZF
0
POLF3
POLF2
POLF1
POLF0
RESET:
0
ICPAR — Input Control Pulse Accumulators Register
$00A8
BIT 7
6
5
4
3
2
1
BIT 0
0
PA3EN
PA2EN
PA1EN
PA0EN
RESET:
0