Analog-to-Digital Converter (ADC)
Data Sheet
MC68HC908SR12MC68HC08SR12 — Rev. 5.0
248
Analog-to-Digital Converter (ADC)
Freescale Semiconductor
15.8.4 ADC Auto-Scan Mode Data Registers (ADRL1–ADRL3)
The ADC data registers 1 to 3 (ADRL1–ADRL3), are 8-bit registers for
conversion results in 8-bit truncated mode, for channels ATD1 to ATD3,
when the ADC is operating in auto-scan mode (MODE[1:0] = 00).
15.8.5 ADC Auto-Scan Control Register (ADASCR)
The ADC auto-scan control register (ADASCR) enables and controls the
ADC auto-scan function.
AUTO[1:0] — Auto-scan Mode Channel Select Bits
AUTO1 and AUTO0 form a 2-bit field which is used to define the
number of auto-scan channels used when in auto-scan mode.
Reset clears these bits.
Address: ADRL1, $005B; ADRL2, $005C; and ADRL3, $005D
Read:
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
RRRRRRRR
Reset:
00000000
R= Reserved
Figure 15-9. ADC Data Register Low 1 to 3 (ADRL1–ADRL3)
Address:
$005E
Read:
00000
AUTO1
AUTO0
ASCAN
Write:
Reset:
00000000
= Unimplemented
R
= Reserved
Figure 15-10. ADC Scan Control Register (ADASCR)
Table 15-4. Auto-scan Mode Channel Select
AUTO1
AUTO0
Auto-Scan Channels
0
ATD0 only
0
1
ATD0 to ATD1
1
0
ATD0 to ATD2
1
ATD0 to ATD3
