Wait for a time, tPGS
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� MC908QB4CDWE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 163/232闋�(y猫)
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鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 724 (CN2011-ZH PDF)
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Memory
MC68HC908QB8 Data Sheet, Rev. 3
34
Freescale Semiconductor
6.
Wait for a time, tPGS.
7.
Write data to the FLASH address being programmed(1).
8.
Wait for time, tPROG.
9.
Repeat step 7 and 8 until all desired bytes within the row are programmed.
10.
Clear the PGM bit (1).
11.
Wait for time, tNVH.
12.
Clear the HVEN bit.
13.
After time, tRCV, the memory can be accessed in read mode again.
NOTE
The COP register at location $FFFF should not be written between steps
5-12, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is written
while HVEN is set.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum, see 18.17
2.6.5 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect blocks of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM
operations.
NOTE
In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and
erased. When all the bits are erased (all 1鈥檚), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are
shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than
$FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass
erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be
erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also
allows entry from reset into the monitor mode.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing
PGM bit, must not exceed the maximum programming time, tPROG maximum.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
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