
Timer Interface B (TIMB)
Features
MC68HC908MR8 — Rev 4.1
Technical Data
Freescale Semiconductor
Timer Interface B (TIMB)
225
Figure 12-1. TIMB Block Diagram
PRESCALER
PRESCALER SELECT
INTERNAL
16-BIT COMPARATOR
PS2
PS1
PS0
16-BIT COMPARATOR
16-BIT LATCH
TCH0H:TCH0L
MS0A
ELS0B
ELS0A
TOF
TOIE
INTERRUPT
CHANNEL 0
TMODH:TMODL
TRST
TSTOP
TOV0
CH0IE
CH0F
CH0MAX
MS0B
16-BIT COUNTER
BUS CLOCK
PTB5/TCH0B
PTB6/TCH1B
16-BIT COMPARATOR
16-BIT LATCH
TCH1H:TCH1L
MS1A
ELS1B
ELS1A
CHANNEL 1
TOV1
CH1IE
CH1F
CH1MAX
PTB5
LOGIC
PTB6
LOGIC
INTERRUPT
LOGIC
INTERRUPT
LOGIC
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0051
TIMB Status/Control Regis-
ter
(TBSC)
Read
:
TOF
TOIE TSTOP
00
PS2
PS1
PS0
Write
:
0TRST
R
Re-
set:
001
0
000
0
$0052
TIMB Counter Register High
(TBCNTH)
Read
:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write
:
RRR
R
RRRR
Re-
set:
000
0
000
0
R= Reserved
Figure 12-2. TIMB I/O Register Summary