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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC908LJ12CPBE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 103/414闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU 12K FLASH 8MHZ 64-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫i€氭€э細 IRSCI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 LCD锛孡VD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 12KB锛�12K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 6x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-LQFP
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 725 (CN2011-ZH PDF)
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Timer Interface Module (TIM)
MC68HC908LJ12 鈥� Rev. 2.1
Technical Data
Freescale Semiconductor
Timer Interface Module (TIM)
191
11.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
11.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
$0032
Timer 2 Channel 0
Register Low
(T2CH0L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
$0033
Timer 2 Channel 1 Status
and Control Register
(T2SC1)
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
$0034
Timer 2 Channel 1
Register High
(T2CH1H)
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Indeterminate after reset
$0035
Timer 2 Channel 1
Register Low
(T2CH1L)
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Indeterminate after reset
Addr.
Register Name
Bit 7
654321
Bit 0
= Unimplemented
Figure 11-2. TIM I/O Register Summary (Sheet 3 of 3)
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