
I/O Registers
MC68HC908JL8/JK8 MC68HC08JL8/JK8 MC68HC908KL8 Data Sheet, Rev. 3.1
Freescale Semiconductor
149
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each
conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH[4:0] form a 5-bit field which is used to select one of the ADC channels. The five channel select
bits are detailed in the following table. Care should be taken when using a port pin as both an analog
and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (See
The ADC subsystem is turned off when the channel select bits are all set to one. This feature allows
for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to
a logic 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 10-1. MUX Channel Select
ADCH4
ADCH3
ADCH2
ADCH1
ADCH0
ADC Channel
Input Select
0
000
0
ADC0
PTB0
0
000
1
ADC1
PTB1
0
001
0
ADC2
PTB2
0
001
1
ADC3
PTB3
0
010
0
ADC4
PTB4
0
010
1
ADC5
PTB5
0
011
0
ADC6
PTB6
0
011
1
ADC7
PTB7
0
100
0
ADC8
PTD3
0
100
1
ADC9
PTD2
0
101
0
ADC10
PTD1
0
101
1
ADC11
PTD0
0
110
0
ADC12
ADC12/T2CLK
0
110
1
Unused(1)
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
:
::::
—
1
101
0
1
101
1
—
Reserved
11
1
0
—
Reserved
11
1
0
1
VDD
(2)
2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the
operation of the ADC converter both in production test and for user applications.
11
1
0
VSS
(2)
11
1
ADC power off