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鍙冩暩璩囨枡
鍨嬭櫉锛� MC908JB16FAE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩锛� 250/332闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 16K FLASH 6MHZ USB 32LQFP
妯欐簴鍖呰锛� 250
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 6MHz
閫i€氭€э細 SCI锛孶SB
澶栧湇瑷倷锛� LED锛孡VD锛孭OR锛孭WM
杓稿叆/杓稿嚭鏁革細 21
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�16K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 384 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 5.5 V
鎸暕鍣ㄥ瀷锛� 鍏ч儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 32-LQFP
鍖呰锛� 鎵樼洡
鐢㈠搧鐩寗闋侀潰锛� 725 (CN2011-ZH PDF)
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Electrical Specifications
MC68HC908JB16 鈥� Rev. 1.1
Technical Data
Freescale Semiconductor
Electrical Specifications
323
Output capacitive load
CL
鈥斺€�
10
pF
PLL frequency list
Rx LO 1
Rx LO 2
Rx LO 3
Rx LO 4
Rx LO 5
鈥�
26.54
26.59
26.64
26.69
26.74
鈥擬Hz
PLL output signal frequency
accuracy
Exclude crystal
OSC tolerance
鈥�
卤100
卤4
鈥�
Hz
ppm
PLL output signal phase
noise level
At
卤1kHz offset
from carrier
鈥斺€�40
鈥�
dBc/Hz
VCO frequency range
26
鈥�
28
MHz
PLL lock duration
channel to
channel(3)
鈥�10
鈥�
ms
Wait/stop mode to
active(4)
鈥�20
鈥�
ms
Duration for Lock bit detection
Within
卤10% final
frequency(5)
鈥�10
鈥�
ms
PLL stop duration
PLL module from
active to disable
mode.
鈥斺€�
1
ms
PLL output sideband
noise level(6)
At offset >4kHz
At offset >42.5kHz
鈥�
鈥�40
鈥�50
鈥攄Bc
PLL output channel
intermodulation products(7)
At offset >42.5kHz
鈥�
鈥�50
鈥�
dBc
Notes:
1. VDDA = 4.0 to 5.5 Vdc, VSSA = 0 Vdc, TA = TL to TH, with the pre-defined programming setting for the PLL
(see 13.10 Pre-Defined VCO Output Frequency Settings) and under steady state condition, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
掳C only.
3. Defined as the total time for PLL module switching from channel-to-channel and the frequency is stable with
卤60ppm. The
reference frequency should be greater than 32kHz.
4. Defined as the total time for PLL module active from wait/stop mode to the frequency is stable with
卤60ppm error. The
reference frequency should be greater than 32kHz.
5. Defined as the total time for PLL Lock bit setup from un-lock to lock state with the frequency is stable with
卤10% error. The
reference frequency should be greater than 32kHz.
6. Side-band component generate from reference frequency modulation on carrier.
7. Noise component generate from adjacent channel carrier when both PLLs are enable.
Characteristic(1)
Condition
Symbol
Min
Typ(2)
Max
Unit
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