
ESCI Arbiter
MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
219
another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced
to 1, resulting in a seized transmission.
If SCI_TxD senses 0 without having sensed a 0 before on RxD, the counter will be reset, arbitration
operation will be restarted after the next rising edge of SCI_TxD.
Figure 14-21. Bit Time Measurement with ACLK = 0
Figure 14-22. Bit Time Measurement with ACLK = 1, Scenario A
Figure 14-23. Bit Time Measurement with ACLK = 1, Scenario B
CP
U
WRITES
SCIACTL
COUNT
ER
STARTS,
COUNT
ER
STOPS,
MEASURED TIME
CPU
READ
S
RES
U
LT
RXD
WIT
H
$
20
ARUN
=
1
AF
IN
=
1
OUT
OF
SCIAD
AT
CPU
WRITES
SCIA
CTL
WITH
$3
0
COUNTER
START
S,
ARUN
=
1
COUNT
ER
STOPS,
AF
IN
=
1
MEASURED TIME
CPU
R
EADS
RESULT
OUT
RXD
OF
SCIADAT
CPU
WRIT
ES
SC
IACT
L
COUNTER
STAR
TS,
COUNTER
STOPS,
MEASURED TIME
CPU
R
EADS
RESULT
RXD
OUT
OF
SCIADAT
AF
IN
=
1
ARU
N
=
1
WI
TH
$30