
Input/Output (I/O) Ports
MC68HC908AP Family Data Sheet, Rev. 4
260
Freescale Semiconductor
Table 16-1. Port Control Register Bits Summary
Port
Bit
DDR
Module Control
Pin
Module
Register
Control Bit
A
0
DDRA0
ADC
ADSCR ($0057)
ADCH[4:0]
PTA0/ADC0
1
DDRA1
PTA1/ADC1
2
DDRA2
PTA2/ADC2
3
DDRA3
PTA3/ADC3
4
DDRA4
PTA4/ADC4
5
DDRA5
PTA5/ADC5
6
DDRA6
PTA6/ADC6
7
DDRA7
PTA7/ADC7
B
0
DDRB0
MBUS
MMCR1 ($0049)
MMEN
PTB0/SDA(1)
1. Pin is open-drain when configured as output. Pullup resistor must be connected when configured as output.
1
DDRB1
PTB1/SCL(1)
2
DDRB2
SCI
SCC1 ($0013)
ENSCI
PTB2/TxD(1)
3
DDRB3
PTB3/RxD(1)
4
DDRB4
TIM1
T1SC0 ($0025)
ELS0B:ELS0A
PTB4/T1CH0(2)
2. Pin has schmitt trigger when configured as input.
5
DDRB5
T1SC1 ($0028)
ELS1B:ELS1A
PTB5/T1CH1(2)
6
DDRB6
TIM2
T2SC0 ($0030)
ELS0B:ELS0A
PTB6/T2CH0(2)
7
DDRB7
T2SC1 ($0033)
ELS1B:ELS1A
PTB7/T2CH1(2)
C
0
DDRC0
IRQ2
INTSCR2 ($001C)
IMASK2
PTC0/IRQ2(2)
1
DDRC1
—
PTC1
2
DDRC2
SPI
SPCR ($0010)
SPE
PTC2/MISO
3
DDRC3
PTC3/MOSI
4
DDRC4
PTC4/SS
5
DDRC5
PTC5/SPSCK
6
DDRC6
IRSCI
IRSCC1 ($0040)
ENSCI
PTC6/SCTxD(1)
7
DDRC7
PTC7/SCRxD(1)
D
0
DDRD0
KBI
KBIER ($001B)
KBIE0
PTD0/KBI0(2)
1
DDRD1
KBIE1
PTD1/KBI1(2)
2
DDRD2
KBIE2
PTD2/KBI2(2)
3
DDRD3
KBIE3
PTD3/KBI3(2)
4
DDRD4
KBIE4
PTD4/KBI4(2)
5
DDRD5
KBIE5
PTD5/KBI5(2)
6
DDRD6
KBIE6
PTD6/KBI6(2)
7
DDRD7
KBIE7
PTD7/KBI7(2)