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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC908AB32CFUE
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 115/392闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU 8MHZ 32K FLASH 64-QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 84
绯诲垪锛� HC08
鏍稿績铏曠悊鍣細 HC08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫i€氭€э細 SCI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 POR锛孭WM
杓稿叆/杓稿嚭鏁�(sh霉)锛� 51
绋嬪簭瀛樺劜鍣ㄥ閲忥細 32KB锛�32K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.5 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x8b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-QFP
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜闈細 726 (CN2011-ZH PDF)
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Timer Interface Module B (TIMB)
MC68HC908AB32 鈥� Rev. 1.1
Technical Data
Freescale Semiconductor
Timer Interface Module B (TIMB)
201
12.5.3 Output Compare
With the output compare function, the TIMB can generate a periodic
pulse with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIMB can set, clear, or toggle the channel pin. Output compares can
generate TIMB CPU interrupt requests.
12.5.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 12.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIMB channel registers.
An unsynchronized write to the TIMB channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIMB overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
When changing to a larger output compare value, enable
channel x TIMB overflow interrupts and write the new value in the
TIMB overflow interrupt routine. The TIMB overflow interrupt
occurs at the end of the current counter overflow period. Writing a
larger value in an output compare interrupt routine (at the end of
the current pulse) could cause two output compares to occur in the
same counter overflow period.
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