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參數資料
| 型號： | MC88LV926DW |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數： | 5/11頁 |
| 文件大?。?/td> | 285K |
| 代理商： | MC88LV926DW |
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
MC88LV926
Table 2. Maximum Ratings(1)
1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
Symbol
Parameter
Limits
Unit
VCC, AVCC
DC Supply Voltage Referenced to GND
–0.5 to 7.0
V
Vin
DC Input Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Vout
DC Output Voltage (Referenced to GND)
–0.5 to VCC +0.5
V
Iin
DC Input Current, Per Pin
±20
mA
Iout
DC Output Sink/Source Current, Per Pin
±50
mA
ICC
DC VCC or GND Current Per Output Pin
±50
mA
Tstg
Storage Temperature
–65 to +150
°C
Table 3. Recommended Operating Conditions
Symbol
Parameter
Limits
Unit
VCC
Supply Voltage
3.3
±0.3
V
Vin
DC Input Voltage
0 to VCC
V
Vout
DC Output Voltage
0 to VCC
V
TA
Ambient Operating Temperature
0 to 70
°C
ESD
Static Discharge Voltage
> 1500
V
Table 4. DC Characteristics (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V)
(1)
1. The MC88LV926 can also be operated from a 3.3V supply. VOH output levels will vary 1:1 with VCC, input levels and current specs will be
unchanged, except VIH; when VCC > 4.0 volts, VIH minimum level is 2.7 volts.
Symbol
Parameter
VCC
Guaranteed Limits
Unit
Condition
VIH
Minimum High Level Input Voltage(1)
3.0
3.3
2.0
V
VOUT = 0.1V or
VCC – 0.1V
VIL
Minimum Low Level Input Voltage
3.0
3.3
0.8
V
VOUT = 0.1V or
VCC – 0.1V
VOH
Minimum High Level Output Voltage
3.0
3.3
2.2
2.5
V
VIN = VIH or
VIL = –24mA
IOH = –24mA
VOL
Minimum Low Level Output Voltage
3.0
3.3
0.55
V
VIN = VIH or
VIL = +24mA
(2)
IOH = +24mA
2. IOL is +12mA for the RST_OUT output.
IIN
Maximum Input Leakage Current
3.3
±1.0
μA
VI = VCC, GND
ICCT
Maximum ICC/Input
3.3
2.0(3)
3. Maximum test duration 2.0ms, one output loaded at a time.
mA
VI = VCC – 2.1V
IOLD
Minimum Dynamic(4) Output Current
4. The PLL_EN input pin is not guaranteed to meet this specification.
3.3
50
mA
VOLD = 1.25V Max
IOHD
3.3
–50
mA
VOHD = 2.35 Min
ICC
Maximum Quiescent Supply Current
3.3
750
μA
VI = VCC, GND
MC88LV926
Low Skew CMOS PLL 68060 Clock Driver
NETCOM
IDT Low Skew CMOS PLL 68060 Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV926
3
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