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參數(shù)資料
| 型號： | MC88LV915TFN |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 88LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 459K |
| 代理商： | MC88LV915TFN |
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MOTOROLA
MC88LV915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88LV915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The
2X_Q output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–
down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high
impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It
will take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88LV915T
PLL
2f
MC88LV915T
PLL
SYSTEM
CLOCK
SOURCE
CPU
CARD
CPU
CARD
MEMORY
CARDS
CMMU
CPU
CLOCK
@ f
CMMU
CPU
2f
PLL
MEMORY
CONTROL
CLOCK @ 2f
AT POINT OF USE
CLOCK @ 2f
AT POINT OF USE
DISTRIBUTE
CLOCK @ f
MC88LV915T
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88LV915T
Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
NETCOM
IDT Low Voltage Low Skew CMOS PLL Clock Driver, 3-State
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88LV915T
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC88LV915TFNR2 | 功能描述:IC DRIVER CLK PLL 100MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88LV926 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL 68060 CLOCK DRIVER |
| MC88LV926DW | 制造商:Integrated Device Technology Inc 功能描述:IDT MC88LV926DW PLL - Rail/Tube 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:FIVE DISTRIBUTED-OUTPUT CLOCK DRIVER, 20 Pin, Plastic, SOP |
| MC88LV926DWR2 | 功能描述:IC DRIVER CLK PLL 66MHZ 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MC88LV926EG | 功能描述:IC PLL CLOCK DRIVER 20-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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