參數(shù)資料
型號(hào): MC88915TFN70
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 11/18頁
文件大小: 401K
代理商: MC88915TFN70
MC88915T
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
27
Figure 1. Pinout: 28-Lead PLCC (Top View)
Table 1. Pin Summary
Pin Name
Number
I/O
Function
SYNC[0]
1
Input
Reference clock input
SYNC[1]
1
Input
Reference clock input
REF_SEL
1
Input
Chooses reference between SYNC[0] and SYNC[1]
FREQ_SEL
1
Input
Doubles VCO internal frequency (low)
FEEDBACK
1
Input
Feedback input to phase detector
RC1
1
Input
Input for external RC network
Q(0–4)
5
Output
Clock output (locked to SYNC)
Q5
1
Output
Inverse of clock output
2x_Q
1
Output
2 x clock output (Q) frequency (synchronous)
Q/2
1
Output
Clock output (Q) frequency
÷ 2 (synchronous)
LOCK
1
Output
Indicates phase lock has been achieved (high when locked)
OE/RST
1
Input
Output enable/asynchronous reset (active low)
PLL_EN
1
Input
Disables phase-lock for low frequency testing
VCC, GND
11
Power and ground pins (note pins 8 and 10 are “analog” supply pins
for internal PLL only)
5
6
7
8
9
10
11
25
24
23
22
21
20
19
432
1
28 27 26
12 13 14 15 16 17 18
Q/2
GND
Q3
VCC
Q2
GND
LOCK
FEEDBACK
REF_SEL
SYNC[0]
VCC(AN)
RC1
GND(AN)
SYNC[1]
FREQ_SEL GND Q0 VCC Q1 GND PLL_EN
OE/RST VCC Q5 GND Q4 VCC 2X_Q
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