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| 型號： | MC88915TFN133R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 181K |
| 代理商： | MC88915TFN133R2 |
MC88915T
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
25
6. Calculation of Total Output–to–Skew between multiple
parts (Part–to–Part skew)
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output pins
only (equally loaded), it does not include PCB trace delays
due to varying loads.
With a 1 M
resistor tied to analog VCC as shown in note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns. To calculate the skew of any given output between
two or more parts, the absolute value of the distribution of
that output given in table 2 must be subtracted and added
to the lower and upper tPD spec limits respectively. For
output Q2, [276 – (–44)] = 320ps is the absolute value of the
distribution. Therefore [–1.05ns – 0.32ns] = –1.37ns is the
lower tPD limit, and [–0.5ns + 0.32ns] = –0.18ns is the upper
limit. Therefore the worst case skew of output Q2 between
any number of parts is |(–1.37) – (–0.18)| = 1.19ns. Q2 has
the worst case skew distribution of any output, so 1.2ns is
the absolute worst case output–to–output skew between
multiple parts.
7. Note 4 explains that the tPD specification was measured and
is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (tPD) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of Figure
3 demonstrate this dependence.
The data presented in Figure 3 is from devices represent-
ing process extremes, and the measurements were also
taken at the voltage extremes (VCC = 5.25V and 4.75V).
Therefore the data in Figure 3 is a realistic representation
of the variation of tPD.
2
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| MC88915TFN160 | 功能描述:IC DRIVER CLK PLL 160MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915TFN160R2 | 制造商:Integrated Device Technology Inc 功能描述:MC88915TFN160R2 - Tape and Reel |
| MC88915TFN55 | 功能描述:IC DRIVER CLK PLL 55MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915TFN70 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915TFN70R2 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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